The present invention relates to a ferroelectric memory device. And more particularly, the invention relates to a ferroelectric memory device having memory cells each of which is made up of a capacitor with an insulating film of ferroelectric material and a MOS transistor.
As a nonvolatile memory realizing high-speed write operation, much attention has been recently focused on a ferroelectric memory which uses a ferroelectric capacitor. In particular, a memory of such a type that each memory cell is made up of a capacitor with an insulating film of ferroelectric material and a MOS transistor and a constant voltage is applied to one of electrodes of the capacitor called a plate has a possibility of being able to realize a nonvolatile memory with nearly the same operating speed and area as those of a dynamic random access memory (DRAM). An example of a basic arrangement of such a prior art ferroelectric memory is shown in FIG. 36. In the drawing, reference symbol MC denotes a memory cell, which is made up of a ferroelectric capacitor with an insulating film of ferroelectric material such as PZT and an NMOS transistor. The remanent polarization of the ferroelectric capacitor stores information. The ferroelectric capacitor is connected at its one end to the NMOS transistor and at the other end (plage electrode) to xc2xd voltage (VCC/2) corresponding to half of a source voltage VCC. For simplicity, only one memory cell MC is illustrated in the illustrated example, but actually a plurality of such memory cells are connected to each of a pair Dt and Db of data lines and are selected by a word line W for data transfer to the data-line pair Dt or Db. Although omitted for simplicity in the drawing, a dummy cell is actually provided to each of the data-line pair Dt and Db. Reference symbol PC denotes a precharge circuit which precharges the data-line pair Dt and Db to a ground voltage VSS. Reference symbol SA denotes a sense amplifier which detects voltages of the data-line pair Dt and Db and amplifies the voltages differentially. Further, though omitted for simplicity in the drawing, a switch is actually provided to the sense amplifier for signal transfer to or from external.
The operation of the above arrangement will be explained with use of a timing chart shown in FIG. 37. In a standby state, a control signal FPC causes the precharge circuit PC to be put in its ON state, so that the data-line pair Dt and Db are precharged to the ground voltage VSS, that is, are in a so-called VSS precharge state. In operation, the control signal FPC causes the precharge circuit PC to be turned OFF. Thus when the word line W has a selected-word-line voltage VCH, the memory cell MC is selected. This causes an NMOS transistor in the memory cell MC to be turned ON, so that a voltage of VCC/2 corresponding to a difference in voltage between a data line Dt and a plate electrode is applied to the ferroelectric capacitor, whereby the remanent polarization is read out as charge to the data line Dt. This varies the voltage on the data line Dt and then a control signal FSA activates the sense amplifier SA, which in turn amplifies the voltage of the data line D with positive feedback to sense data. Though not illustrated in FIG. 37, when the data sensed by the sense amplifier SA is output externally, read operation is carried out. Further, when the voltage of the data line is used as a write voltage in accordance with externally entered data, write operation is carried out. When the word line W is lowered to turn OFF the NMOS transistor in the memory cell MC, rewrite operation to the memory cell MC is carried out. Thereafter, the control signal FSA stops the operation of the sense amplifier SA, the control signal FPC turns ON a precharging switch, thus returning the current state to the standby mode.
The operation of the ferroelectric capacitor in the standby mode will be explained with use of a hysteresis characteristic shown in FIG. 38. In the drawing, horizontal axis denotes a voltage applied to the ferroelectric capacitor with the voltage of the plate electrode as a reference, and vertical axis denotes a charge amount stored in the ferroelectric capacitor including polarization. In such a condition that no voltage is applied to the ferroelectric capacitor in the standby state, the ferroelectric capacitor retains remanent polarization and takes a position of either point PS0 or PS1 in FIG. 38 depending on data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d stored in the capacitor. When it is desired to read out a signal from the memory cell MC to the data line D, the data line D is precharged to xe2x88x92VCC/2 with the voltage of the plate electrode as a reference, so that a data-line capacitance CD is represented by load lines LL0 and LL1 having a gradient of xe2x88x92CD in FIG. 38. Intersections of the load lines and hysteresis characteristics are points which the ferroelectric capacitor takes in its read mode. Meanwhile, the write operation is carried out when the capacitors takes a point PW0 or PW1 in FIG. 38 with the data line D having the voltage of VSS or VCC.
As has been explained above, in the ferroelectric memory device, the voltage is applied to the ferroelectric capacitor to cause the reverse polarization to generate charge on the data line.
The following schemes which relate to the present application and are directed to DRAMs have been disclosed.
Disclosed in JP-A-62-180591 is a scheme of dividing a precharge voltage of a data-line pair into two in order to reduce array noise.
Also disclosed in JP-A-5-135580 is a scheme of transferring charge between sense amplification groups in order to reduce a charge amount consumed in rewrite and precharge operation.
Further disclosed in JP-A-4-184787 is a scheme of dividing a precharge voltage of a data-line pair in a memory cell array into two to transfer charge between two data-line pairs. The present application will be explained in association with these schemes.
In a ferroelectric memory device, in order to generate a signal voltage on a data line, a voltage must be applied to a ferroelectric capacitor. Thus, when a plate is set to have a constant voltage, it is impossible to employ the scheme which reads out a signal with the data line precharged to VCC/2 and is widely used in DRAM fields, that is, a so-called VCC/2 precharge scheme. And the ferroelectric memory device has drawbacks including the three problems discussed below, when compared to a DRAM of the above VCC/2 precharge scheme.
First, the device has a large array noise. More specifically, a ferroelectric memory employs a VSS precharge scheme (or VCC precharge scheme). Thus a signal is read-out from one memory cell in all data lines, the voltage varies from VSS toward a higher level (from VCC toward a lower level in the VCC precharge scheme). For this reason, large coupling noise takes place in non-selected word lines or wells coupled capacitively with them. The noise is again capacitively coupled with the data lines to fluctuate the voltages of the data lines. Meanwhile, when a voltage at a storage-node in a selected memory cell drops, a plate voltage is lowered through a ferroelectric capacitor. This voltage applied to the ferroelectric capacitor in the memory cell becomes small, so that a part of the remanent polarization of ferroelectric material to be read out as charge becomes small in amount, thus decreasing an S/N ratio. In the VSS precharge scheme, when a voltage between the data-line pair is amplified by a sense amplifier, one of the voltages of the data lines in the pair is charged to VCC by the sense amplifier with a large variation, whereas the other voltage is discharged to VSS with a small variation. For this reason, great coupling noise takes place in all nodes capacitively coupled with the data-line pair, increasing the voltage. The noise is again capacitively coupled with the data lines so that differences in the magnitude of coupling capacitance between the data line pairs result in differential noise, thus reducing the S/N ratio. For such noise, DRAM is described in detail in a book entitled xe2x80x9cAdvanced Electronics I-9, Ultra LSI Memoriesxe2x80x9d, written by Kiyoo Itoh, issued from Baifuukan, 1994, Chapter 3. The discussion in the book also holds true for the ferroelectric memory. Further, the voltage of the data line discharged to VSS is boosted due to coupling, the MOS transistor of the memory cell connected to the data line discharged to VSS is conducted so that VSS is input to the ferroelectric capacitor, with a danger of destroying the polarization data.
Second, power consumption is great. Either one of the data lines Dt and Db in pair is charged to VCC from VSS during its amplification, and is discharged again to VSS during its precharge operation. The amount of charge then consumed is CDxc3x97VCC per data line pair, when the data line capacitance is CD. In the VCC/2 precharge scheme, one of the data lines in pair is charged from VCC/2 to VCC, the other is discharged from VCC/2 to VSS, and precharge is carried out through charge share between the data lines in pair. Therefore, a consumed charge amount per data-line pair is CDxc3x97VCC/2. Thus the VSS precharge scheme requires a power necessary for charge and discharge of the data lines to be twice as high as that of the VCC/2 precharge scheme.
Third, the characteristics of the ferroelectric capacitor are largely deteriorated by its fatigue and imprint. When read operation is carried out in the VSS precharge mode, the polarization direction of the ferroelectric capacitor having xe2x80x9c1xe2x80x9d so far written therein is reversed. Further, since VCC is applied to rewrite xe2x80x9c1xe2x80x9d, the polarization direction is again reversed. The repetition of the above operation results in characteristic deterioration caused by the fatigue. Meanwhile, the repetitive application of VSS results in that the characteristics of the capacitor having xe2x80x9c0xe2x80x9d written therein are deteriorated by. the imprint. That is, the fatigue or imprint becomes remarkable depending on the written data. Rewrite operation is carried out for all the memory cells on the selected word line and the read operation is generally carried out more frequently than the reverse write operation, with the result that the same data is often repetitively written. This leads to the aforementioned fatigue and imprint phenomena.
It is an object of the present invention to solve problems in the above prior art ferroelectric memory device.
A first object of the present invention is to realize a high S/N ratio and stable operation by minimizing an array noise generated when a memory cell using a ferroelectric capacitor generates a signal voltage.
A second object is to realize a low necessary power by reducing the amount of charge consumed for rewriting and precharging.
A third object is to realize a high reliability by suppressing fatigue and imprint of a ferroelectric capacitor.
Other objects will become clear from description of embodiments which follow.
In accordance with the present invention, the above objects are attained by providing a ferroelectric memory device which includes first and second memory cells (MCl) each having a ferroelectric capacitor with an insulating film of ferroelectric material and having a transistor connected to one of electrodes of the ferroelectric capacitor, a first data line (D0t) connected to said transistor of said first memory cell, a second data line (D1t) connected to said transistor of said second memory cell, word lines connected to control electrodes of the transistors of said first and second memory cells, and first and second sense amplifiers (SA0, SA1) provided as associated with said first and second data lines; and which further comprises a first precharge circuit (PC0) for connecting said first data line to a first precharge potential (Vss); and a second precharge circuit (PC1) for connecting said second data line to a second precharge potential (Vcc); and wherein a potential (Vcc/2) of the other electrodes of said ferroelectric capacitors of said first and second memory cells is set to be between said first and second precharge potentials.
More desirably, a difference between the potential of the other electrodes of said ferroelectric capacitors and said first precharge potential is equal to a difference between the potential of the other electrode of said ferroelectric capacitors and said second precharge potential. That is, an average of the first and second precharge potentials is set at a voltage close to an average of a write voltage of xe2x80x9c1xe2x80x9d and a write voltage of xe2x80x9c0xe2x80x9d. More in detail, the above first to third objects are attained by using first to third means which follow respectively.
The first means comprises word lines connected to control electrodes of transistors in said first and second memory cells (refer to FIGS. 1 and 2). Thereby noise from the first data line and noise from the second data line are cancelled from each other to cancel noise toward the word lines, thus attaining the first object.
A scheme of dividing the precharge voltages into two in DRAM is disclosed in JP-A-62-180591 or JP-A-4-184787. When a similar scheme to the above is used for such a ferroelectric memory device as to require Vcc precharge or Vss precharge, there can be satisfied an essential requirement inherent in a ferroelectric memory device that a voltage be applied to a ferroelectric capacitor at word-line activation. With respect to DRAM, it is common sense that, when factors including S/N ratio, power consumption and operational speed are generally considered, a VCC/2 precharge scheme is excellent. In such a ferroelectric memory device that a plate voltage is set to be constant, however, since the VCC/2 precharge scheme cannot be employed, such a scheme becomes effective means.
The second means comprises:
first and second memory cells each including a ferroelectric capacitor with an insulating film of ferroelectric material and including a transistor connected to one of electrodes of the ferroelectric capacitor;
first and second data lines (D0tS, D0TC) connected to said corresponding first and second memory cells;
a first precharge circuit (PC0S) for connecting said first data line to a first precharge potential;
a second precharge circuit (PC0C) for connecting said second data line to a second precharge potential;
a first sense amplifier (SA0S) made up of two P-channel MOS transistors cross-coupled for detecting data from said first memory cell appearing on said first data line;
a second sense amplifier (SA0C) made up of two N-channel MOS transistors cross-coupled for detecting data from said second memory cell appearing on said second data line;
a first driving line (CSPS) for driving said first sense amplifier;
a second driving line (CSNC) for driving said second sense amplifier; and
a switch circuit (CSD) for allowing continuity between said first and second driving lines after potentials (Vss, Vcc) are supplied to said first and second driving lines to put said first and second sense amplifiers in their non-driving state respectively and then the supply is stopped (refer to FIGS. 20 and 21).
With the above arrangement, the second object is attained. A scheme of performing charge transfer between two groups of sense amplifiers in DRAM is disclosed in JP-A-5-135580. In this prior art, charge transfer is carried out between the sense amplifier group after data line amplification and the sense amplifier group for the next amplification. For this reason, this is effective when the sense amplifier groups are sequentially activated in a given order as in the self-refresh operation of DRAM, but its applicable operation is limited. For example, when the identical sense amplifier group is activated twice continuously, this scheme cannot be used. Meanwhile, in the present means, since charge transfer is carried out between the sense amplifier groups of different precharge voltages, this scheme can be applied to usual random access operation. Further, with respect to DRAM, JP-A-4-184787 discloses a scheme of grouping precharge voltages of a data line pair in a memory cell array into two for data transfer between two of data line pairs. When such a scheme is applied to a ferroelectric memory device, a requirement that a voltage be applied to a ferroelectric capacitor at word-line activation, can be attained. For such a ferroelectric memory device as not to employ the VCC/2 precharge scheme, this scheme is effective means.
The third means comprises:
memory cells each including a ferroelectric capacitor with an insulating film of ferroelectric material and including a transistor connected to one of electrodes of the ferroelectric capacitor;
a data line (D0t) connected to the memory cells; and
a precharge circuit (PC0) for precharging said data line to a first or second precharge potential, and
wherein the potential (Vcc/2) of the other electrodes of said ferroelectric capacitors of said memory cells is set to be between said first precharge potential (Vss) and said second precharge potential (Vcc), and said precharge circuit alternately precharges said data line with said first and second precharge potentials (refer to FIG. 26).
Thereby, two sorts of Vss and Vcc precharge schemes can be applied with a high possibility to the identical memory cell, thus attaining the third object.
Further, means corresponding to a combination of the above means enables simultaneous attainment of a combination of the effects of the above means.